https://blog.carrese.eu/ Daily practical notes on STM32, STM8, STM32U5, STM32F4, Embedded C/C++, firmware debugging, testing and product delivery. en Mon, 06 Jul 2026 06:21:31 +0000 https://blog.carrese.eu/articles/2026-07-06-stm32-crc-peripheral-hardware-checksum/ https://blog.carrese.eu/articles/2026-07-06-stm32-crc-peripheral-hardware-checksum/ Mon, 06 Jul 2026 08:00:00 +0000 A practical register-level guide to the STM32 CRC calculation unit: polynomial configuration, data alignment, one-shot and streaming usage, bootloader integrity checks, and communication CRC. STM32CRCData IntegrityBootloaderEmbedded https://blog.carrese.eu/articles/2026-07-05-git-workflow-firmware-teams/ https://blog.carrese.eu/articles/2026-07-05-git-workflow-firmware-teams/ Sun, 05 Jul 2026 08:00:00 +0000 A practical, battle-tested Git branching strategy and workflow for embedded firmware teams: handling binary files, CI integration, release management, and avoiding the Git mess that plagues every hardware project. GITPROCESSTOOLINGFIRMWARECICD https://blog.carrese.eu/articles/2026-07-04-stm32-usart-interrupt-register-level/ https://blog.carrese.eu/articles/2026-07-04-stm32-usart-interrupt-register-level/ Sat, 04 Jul 2026 08:00:00 +0000 Complete register-level guide to STM32F4 USART interrupt-driven TX/RX: baud rate generation, data format, TXE/RXNE/TC interrupt management, overrun/framing error handling, ring buffer implementation, and a practical GPS module communication example. STM32USARTRegister-LevelInterruptsSTM32F4Embedded https://blog.carrese.eu/articles/2026-07-03-building-embedded-contractor-client-network/ https://blog.carrese.eu/articles/2026-07-03-building-embedded-contractor-client-network/ Fri, 03 Jul 2026 08:00:00 +0000 A practical guide to building a steady stream of embedded firmware contracting opportunities: outreach strategies, networking, lead qualification, and maintaining long-term client relationships. CLIENTSFREELANCENETWORKCONTRACTOR https://blog.carrese.eu/articles/2026-07-02-stm32-spi-register-master-full-duplex/ https://blog.carrese.eu/articles/2026-07-02-stm32-spi-register-master-full-duplex/ Thu, 02 Jul 2026 08:00:00 +0000 Complete register-level guide to configuring STM32 SPI in full-duplex master mode on STM32F4: clock polarity/phase, baud rate, data frame format, NSS management, and interrupt-driven data exchange with C code. STM32SPIRegister-LevelSTM32F4Embedded https://blog.carrese.eu/articles/2026-07-01-firmware-specifications-client-engineer/ https://blog.carrese.eu/articles/2026-07-01-firmware-specifications-client-engineer/ Wed, 01 Jul 2026 08:00:00 +0000 Most firmware specifications are either too vague for engineers or too technical for clients. Here is a practical framework for writing specs that both sides actually read and use. SPECSCLIENTSCOMMUNICATIONPROCESS https://blog.carrese.eu/articles/2026-06-29-firmware-code-review-culture/ https://blog.carrese.eu/articles/2026-06-29-firmware-code-review-culture/ Mon, 29 Jun 2026 08:00:00 +0000 Code reviews in firmware teams often degenerate into rubber-stamping or pedantic style wars. Here is a practical system for reviews that actually catch bugs, share knowledge, and ship faster. CODE-REVIEWTEAMPROCESSEMBEDDED https://blog.carrese.eu/articles/2026-06-27-stm32-pvd-programmable-voltage-detector/ https://blog.carrese.eu/articles/2026-06-27-stm32-pvd-programmable-voltage-detector/ Sat, 27 Jun 2026 08:00:00 +0000 STM32 Programmable Voltage Detector (PVD) at register level: threshold selection, interrupt and event mode, brownout detection without an external supervisor IC. Practical example on STM32G4 and STM32U5. STM32PVDBrownoutPower ManagementEmbedded https://blog.carrese.eu/articles/2026-06-27-firmware-estimates-contractor-guide/ https://blog.carrese.eu/articles/2026-06-27-firmware-estimates-contractor-guide/ Sat, 27 Jun 2026 08:00:00 +0000 Firmware estimation is notoriously unreliable. Here is a practical framework for embedded contractors to estimate firmware tasks accurately, handle scope creep, and communicate timelines to clients without overpromising. CAREERFIRMWAREESTIMATIONCONTRACTORMANAGEMENT https://blog.carrese.eu/articles/2026-06-25-stm32-i2c-master-register-error-handling/ https://blog.carrese.eu/articles/2026-06-25-stm32-i2c-master-register-error-handling/ Thu, 25 Jun 2026 08:00:00 +0000 STM32 I2C master mode at register level: timing calculation, transmit/receive sequence, NACK handling, arbitration lost, bus recovery, and a practical sensor-read example for G4, H7, and U5 series. STM32I2CRegister-LevelError HandlingEmbedded https://blog.carrese.eu/articles/2026-06-23-stm32-mpu-memory-protection-configuration/ https://blog.carrese.eu/articles/2026-06-23-stm32-mpu-memory-protection-configuration/ Tue, 23 Jun 2026 08:00:00 +0000 STM32 MPU (Memory Protection Unit) configuration at register and CMSIS level: set up region attributes, subregions, and privilege separation for production firmware on Cortex-M3/M4/M7/M33. STM32MPUCortex-MMemory ProtectionEmbeddedFirmware https://blog.carrese.eu/articles/2026-06-22-stm32-hardfault-debug-register-level/ https://blog.carrese.eu/articles/2026-06-22-stm32-hardfault-debug-register-level/ Mon, 22 Jun 2026 08:00:00 +0000 Practical guide to recovering HardFault root cause on STM32 by reading CFSR, HFSR, and stacked context from firmware — no JTAG/SWD needed. STM32Cortex-MFaultDebugging https://blog.carrese.eu/articles/2026-06-21-stm32-flash-option-bytes-rdp-otp/ https://blog.carrese.eu/articles/2026-06-21-stm32-flash-option-bytes-rdp-otp/ Sun, 21 Jun 2026 08:00:00 +0000 STM32 flash option bytes: configure read protection (RDP Level 0/1/2), BOR threshold, boot mode, and one-time programmable (OTP) area at register level. Practical examples for STM32F4, L4, G4, and U5. STM32FlashOption BytesRDPBOROTPBootSTM32F4STM32L4STM32G4Embedded https://blog.carrese.eu/articles/2026-06-20-stm32-rtc-backup-domain-tamper-wakeup/ https://blog.carrese.eu/articles/2026-06-20-stm32-rtc-backup-domain-tamper-wakeup/ Sat, 20 Jun 2026 08:00:00 +0000 STM32 RTC backup domain: configure VBAT-powered RTC calendar, backup registers, tamper detection with timestamp, and wake-up from STOP/STANDBY modes. Register-level examples for STM32F4, L4, G4, U5. STM32RTCBackup DomainVBATTamperWake-UpLow-PowerSTM32F4STM32L4STM32G4Embedded https://blog.carrese.eu/articles/2026-06-19-stm32-dac-timer-trigger-dma-waveform/ https://blog.carrese.eu/articles/2026-06-19-stm32-dac-timer-trigger-dma-waveform/ Fri, 19 Jun 2026 08:00:00 +0000 STM32 DAC with timer-triggered DMA: configure the DAC at register level, use TIM6 as update trigger, and stream arbitrary waveform samples via circular DMA without CPU intervention. Practical STM32F4/G4/L4 examples. STM32DACDMATimerSTM32F4STM32G4Embedded https://blog.carrese.eu/articles/2026-06-18-stm32-fpu-configuration-register-level/ https://blog.carrese.eu/articles/2026-06-18-stm32-fpu-configuration-register-level/ Thu, 18 Jun 2026 08:00:00 +0000 STM32 FPU configuration at register level on Cortex-M4 and M7: enabling the FPU via CPACR, lazy stacking, compiler ABI flags, and the most common hard fault causes. Practical guide for senior embedded engineers. STM32FPUCortex-M4Cortex-M7ARMEmbedded https://blog.carrese.eu/articles/2026-06-17-stm32-system-bootloader-uart-dfu/ https://blog.carrese.eu/articles/2026-06-17-stm32-system-bootloader-uart-dfu/ Wed, 17 Jun 2026 08:00:00 +0000 STM32 System Memory Bootloader: access the ROM bootloader via USART, I2C, SPI, CAN FD, and USB DFU. Practical guide to production programming, field updates, and brick recovery without a debugger. STM32BootloaderUARTDFUProductionField-Upgrade https://blog.carrese.eu/articles/2026-06-16-stm32-clock-security-system-css/ https://blog.carrese.eu/articles/2026-06-16-stm32-clock-security-system-css/ Tue, 16 Jun 2026 08:00:00 +0000 STM32 Clock Security System (CSS): detect HSE failure at runtime, handle NMI, and implement a safe fallback strategy for production firmware. STM32RCCCSSHSENMISafety https://blog.carrese.eu/articles/2026-06-15-stm32-iwdg-watchdog-production/ https://blog.carrese.eu/articles/2026-06-15-stm32-iwdg-watchdog-production/ Mon, 15 Jun 2026 08:00:00 +0000 Master the STM32 Independent Watchdog (IWDG): LSI clock, prescaler, reload register, window option, debug freeze, proper feeding patterns, reset-cause detection, and a complete production-grade template for STM32F4/STM32U5. STM32IWDGWatchdogSTM32F4STM32U5Embedded https://blog.carrese.eu/articles/2026-06-14-stm32h7-dcache-dma-coherency/ https://blog.carrese.eu/articles/2026-06-14-stm32h7-dcache-dma-coherency/ Sun, 14 Jun 2026 08:00:00 +0000 Master STM32H7 data cache maintenance for DMA buffers: SCB_CleanDCache, SCB_InvalidateDCache, SCB_CleanInvalidateDCache, MPU memory type configuration, and a practical template to avoid stale-data corruption on Cortex-M7 peripherals. STM32STM32H7DMAD-CacheCortex-M7MPUEmbedded https://blog.carrese.eu/articles/2026-06-13-stm32-dual-bank-flash-swap-ota/ https://blog.carrese.eu/articles/2026-06-13-stm32-dual-bank-flash-swap-ota/ Sat, 13 Jun 2026 08:00:00 +0000 Configure STM32 dual-bank flash mode: option byte programming for bank organization, bank swapping via FLASH_OPTCR, interrupt vector table relocation, and a complete safe OTA update architecture with fallback on STM32G4/L4/U5. STM32FlashDual BankOTABootloaderG4L4U5 https://blog.carrese.eu/articles/2026-06-12-stm32-rcc-clock-config-pll-register/ https://blog.carrese.eu/articles/2026-06-12-stm32-rcc-clock-config-pll-register/ Fri, 12 Jun 2026 08:00:00 +0000 Configure the STM32F4 clock tree entirely through registers: HSI/HSE oscillator startup, PLL configuration (M/N/P/Q dividers), AHB/APB prescalers, and glitch-free system clock switching. Register-level walkthrough with a practical 168 MHz setup example. STM32RCCClockPLLRegister-LevelSTM32F4 https://blog.carrese.eu/articles/2026-06-11-stm32-exti-external-interrupt-register-level/ https://blog.carrese.eu/articles/2026-06-11-stm32-exti-external-interrupt-register-level/ Thu, 11 Jun 2026 08:00:00 +0000 Configure STM32 EXTI external interrupts without HAL: SYSCFG_EXTICR GPIO mapping, EXTI rising/falling edge triggers, interrupt mask, pending flag clearing, and NVIC integration. Register-level walkthrough on STM32F4 with a practical push-button example. STM32EXTIInterruptGPIORegister-LevelNVIC https://blog.carrese.eu/articles/2026-06-10-stm32-advanced-timer-pwm-deadtime-complementary/ https://blog.carrese.eu/articles/2026-06-10-stm32-advanced-timer-pwm-deadtime-complementary/ Wed, 10 Jun 2026 08:00:00 +0000 Configure TIM1/TIM8 advanced-control timers for centre-aligned PWM with dead-time insertion and complementary CHxN outputs. Register-level walkthrough on STM32F4: BDTR, CCMR, CCER, ARR/CCR, break inputs, and a full half-bridge motor-control example. STM32TIM1PWMDead-TimeRegister-Level https://blog.carrese.eu/articles/2026-06-09-stm32-bxcan-filter-config-message-handling/ https://blog.carrese.eu/articles/2026-06-09-stm32-bxcan-filter-config-message-handling/ Tue, 09 Jun 2026 08:00:00 +0000 Complete guide to STM32 bxCAN filter banks: 32-bit vs 16-bit scaling, mask vs list mode, HAL_CAN and register-level configuration, message transmission/reception, and a practical dual-board communication example. Embedded